In the advent of bipolar complementary metal-oxide-silicon (BiCMOS) technology many circuit designs have been converted to include both bipolar transistors and complementary metal-oxide-silicon (CMOS) devices. In this way, circuit designers can take advantage of the speed of emitter-coupled logic circuits (ECL) and the small size and low power consumption properties of CMOS storage elements.
ECL memory cells are typically very fast and CMOS memory cells are typically low power and small. Consequently, it is desirable to combine both of these properties by designing a BiCMOS memory cell. This is particularly true as memory capacity increases. However, although there are many memory cell designs made-up of solely ECL or CMOS devices, there are few BiCMOS memory cell designs available.
One prior art BiCMOS memory cell design disclosed by Drew Wingard, et al. entitled "Circuit Techniques for Large CSEA SRAM's" in the IEEE Journal of Solid State Circuits, Vol 27, no. 6, June 1992, is shown in FIG. 1. Referring to FIG. 1, the memory cell is shown in typical array configuration including rows and columns of memory cells, i.e. C11, C12, C13, and C21. C11 shows the memory cell in detail. It should be noted that the write circuitry for C11 has been omitted so as to simplify explanation of the memory cell.
As can be seen, each memory cell includes a CMOS storage portion comprising two CMOS inverters connected such that the input of each inverter is coupled to the output of the other. MOS devices P1 and N1 comprise the first inverter and P2 and N2 the other inverter. The inverters are coupled between two voltage potentials, VSS and RWL1, (referred to as the read word (RW) line). The first voltage potential, VSS, is fixed at approximately zero volts, i.e. ground. The second potential, RWL1 is a variable potential line. This RW line is driven between a logic high voltage potential, approximately (VDD-VD.sub.DIODE DROP), and a low voltage potential, approximately (VDD-2.times.V.sub.DIODE DROP). The output of the CMOS storage cell, node 30, (also referred to as the storage node of the cell) is taken at the output of one of the inverters.
The base-emitter junction of npn bipolar transistor Q11 is coupled between node 30 and bit line BL1. Q11 functions to transfer the data stored in the cell to the bit line. To transfer data from the cell to the bit line, the RW line is driven to a voltage potential corresponding to a high logic level. Since Q11 is an emitter follower, the binary data on its base is seen at its emitter, and consequently on BL1.
As can be seen in FIG. 1, a memory array comprising the BiCMOS memory cell described above has many rows and columns of BiCMOS storage cells. All of the transfer devices in the same column have their emitters coupled to the same bit line. Referring to FIG. 1 the emitters of Q11, Q12, and Q13 are coupled to BL1. All of the same storage cells in a particular row are connected between the same RW line and ground, i.e. C11 and C21 are both coupled between RWL1 and VSS.
The array functions such that only a row, or word, of data is transferred to the bit lines when one of the RW lines is driven high. If the array has N bit lines, an N-bit word is transferred. For the array shown in FIG. 1, two bit lines are shown so the output of the array is a 2-bit word.
Each bit line has its own corresponding sense amplifier which compares the voltage on the bit line, i.e. the data from the cell, to a reference voltage; i.e. sense amplifier 1 corresponds to BL1 and sense amplifier 2 corresponds to BL2. The sense amplifier responds to the voltage on the bit lines and outputs a voltage potential corresponding to that sensed logic state.
One problem with the above described BiCMOS memory cell is related to the speed at which data can be read from it. A finite amount of delay occurs from the time a RW line is driven high to the time a change is sensed on the bit line of a sense amplifier. This read delay time is primarily due to the resistive and capacitive (RC) loading on the RW and bit lines. High RC loading results in slow signal response times. The RC loading of these lines depend on several factors.
One factor is related to the number of memory cells that a RW or bit line is coupled to within the array; the more memory cells that a bit or RW line is coupled to, the more RC loading. In particular, the RC loading presented by the resistance associated with P2 and the capacitance associated with the drain of P2, interconnect wiring, and the base of Q11 add significantly to the delay during read access. Further, since there are many rows and columns within a memory array, the capacitive loading on bit and RW lines is high. Another factor affecting the RC loading is the length of the bit and RW lines; the longer an interconnect line is, the higher its associated line resistance and capacitance. Since bit and RW lines are relatively long, they tend to be high capacitive lines.
The above RC loading factors impact the speed at which the BiCMOS memory cell shown in FIG. 1 can be read. In addition, for a given cell size and current drive, the larger the peak voltage of the signal driving the RW and bit lines the slower read times will be. The prior art memory cell shown in FIG. 1 functions such that single-ended voltages are presented to the sense amplifier. Thus, the voltage swing on the bit lines tend to be relatively large in order to be sensed reliably.
Consequently, although the BiCMOS memory cell described above can be read faster than a complementary metal-oxide-silicon (CMOS) memory cell, it is significantly slower than a fully differential emitter-coupled logic (ECL) memory cell.
Another problem associated with the prior art BiCMOS memory cell shown in FIG. 1 results when low data is being presented to the transfer transistor from the memory cell. Since the CMOS storage cell is coupled between the RW line and ground, when low data is presented to the transfer transistor Q11, its base is at a voltage potential approximately equal to ground. The ground potential on the base of the Q11 is compared to a higher reference voltage on its emitter, (coupled to BL1 through the sense amplifier). With its base at ground and its emitter at a high voltage potential, Q11's base-emitter junction is strongly reverse biased. This reverse biasing has an adverse effect on the beta of the transfer device. Specifically, hot electron injection occurring in the base-emitter junction over a long period of time causes beta degradation. Reduced betas may impact the ability of the transfer device to transfer the correct data from the memory cell to the bit line and can lead to incorrect output data.
One BiCMOS design which avoids this reverse biasing problem is disclosed in U.S. Pat. No. 4,933,899; shown in FIG. 2. In this BiCMOS memory cell design, the base-emitter junction of the bipolar transfer transistor is isolated from the CMOS storage cell portion of the memory cell by a buffer circuit. Referring to FIG. 2, the CMOS storage cell comprising P1, P2, N1 and N2 is coupled between two fixed voltage potentials; a CMOS logic high voltage potential (VDD) and and a CMOS logic low level voltage (VSS), instead of the variable RW line and ground (as seen in FIG. 1). The storage nodes of the CMOS storage cell, nodes 1 and 2 are coupled to a buffer circuit.
The buffer circuit comprises series-coupled PMOS devices P3 and P4 and series-coupled devices P5 and P6. Further, the gates of P4 and P5 are coupled to node 1 and the gates of P3 and P6 are coupled to node 2. Each pair of series-coupled devices are coupled between RWL and a reference voltage (VREF). VREF is greater than ground. In contrast to the BiCMOS memory cell shown in FIG. 1, the bases of transfer device Q11 and Q12 is coupled to the buffer circuit instead of the storage cell. With the memory cell designed in this manner, when a low voltage is sensed, the base of the transfer device is at a voltage approximately equal to VREF, (instead of at ground as in FIG. 1). As a result, the reverse bias voltage on the base-emitter junction of the transfer device in the prior art memory cell shown in FIG. 2 is eliminated. Thus, no beta degradation due to hot electron injection occurs.
The prior art memory cell shown in FIG. 2 reduces the beta degradation problem associated with large reverse biasing on the transfer device. However, this design does not make a significant impact in reducing capacitive related delay times associated with reading the BiCMOS memory cell; particularly, since the RWL is still a variable voltage signal and a delay is still presented by P5 and Q11 (or P3 and Q12), in addition to the capacitance associated with the RW line.
In addition, the prior art memory cell design shown in FIG. 2 is a pseudo-differential memory cell and requires much larger RW and bit line voltage swings in order to be reliably sensed. Since it is a pseudo-differential memory cell, only one of the bit lines supplies the signal while the other provides the cell reference. For example, as shown in FIG. 2, when a read operation is being performed, the voltage potential on BL/ is held at a reference voltage while BL moves in response to the RW line, or BL is held at a reference voltage while BL/ moves, (depending on the state stored in the memory cells). However, it is often desirable to have a differential memory cell design in which the memory cell outputs a signal and the inverse of the given signal, referred to as a fully differential signal. One advantage of a fully differential memory cell is that the swing on the bit lines can be less than half that of the single-ended or pseudo-differential cell.
The present invention is an improved differential BiCMOS memory cell that reduces read delay times by sensing differential current changes, (as opposed to large voltage changes) on high fan-out bit lines. The bit line voltage swing of the present invention is at least an order of magnitude less than that of the any prior art BiCMOS design. Further, the memory cell design of the present invention is enhanced so as to reduce the RC loading commonly seen in prior art memory cells.